The present invention relates to s semiconductor memory device, and more particularly to a technique effectively applied to a semiconductor memory device such as a DRAM etc. adopting a connection method, which is called a two cells/bit method employing a so-called one-intersection cell.
According to examinations by the inventors of the present invention, the following techniques are available for the DRAM as an example of the semiconductor memory device.
For example, with respect to the DRAM, there are an open bit-line method and a folded bit-line method as methods of connecting a sense amplifier and a bit-line pair. The former open bit-line method is one in which two bit lines to be connected to one sense amplifier are separately connected on both sides to put the sense amplifier therebetween. By the open bit-line method, a so-called one-intersection memory cell structure is formed in which memory cells MC are connected to all of the intersections between the bit-line pair BL and /BL and a word line WL. The theoretical minimum cell area of the one-intersection memory cell is 4F2 (2F×2F) in terms of a memory-cell-area representing method employing the value “F” of half the pitch of the word line. As a typical example of the one-intersection memory cell, the one having an area of about 6F2 (2F×3F) has been reported in the academic conference. The latter folded bit-line method is one in which two bit lines to be connected to one sense amplifier are folded and connected in the same direction relative to the sense amplifier. In the folded bit-line method, a so-called two-intersection memory cell structure is formed in which the memory cells MC are connected to half of the intersections between the bit-line pair BL and /BL and the word line WL. The theoretical minimum cell area of the two-intersection memory cell is 8F2 (4F×2F) in terms of the memory-cell-area representing method employing the value “F” of half the pitch of the word line.
The former open bit-line method has a high risk of obtaining error information from the memory cell since the fluctuation in a word line potential is applied to only one of the bit-line pair due to parasitic capacitance applied between the word line and the bit line. In contrast to this, the latter folded bit-line method can cancel the noise between the bit lines since the fluctuation in a word line potential (noise) is equally applied to both of the bit-line pair via the parasitic capacitance applied between the word line and the bit line. Consequently, the folded bit-line method is one suitable for the DRAM that detects and amplifies the voltage of small signal from the memory cell and, for example, is more frequently used in the DRAM of 64 kbit or lager.
Meanwhile, in DRAM employing the connection method called a two cells/bit method, there is a connection method generally called a two-intersection cell·two cells/bit method among the connection methods of the memory cells arranged at the intersections between the word lines and the bit lines. This two-intersection cell·two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a first word line; a second memory cell is connected to the intersection between the other of the bit-line pair and a second word line; and the two memory cells correspond to one bit.
Additionally, a memory cell of the one-intersection cell·two cells/bit method is also proposed similarly. This one-intersection cell·two cells/bit method has a structure in which: a first memory cell is connected to the intersection between one of the bit-line pair and a word line; a second memory cell is connected to the intersection between the other of the bit-line pair and the same word line; and the two memory cells correspond to one bit.
Note that as techniques concerning the above-mentioned DRAM employing the one-intersection cell·two cells/bit method, there are recited, for example, Japanese Patent Laid-Open Nos. 61-34790, 55-157194, 8-222706 (U.S. Pat. No. 5,661,678 corresponding thereto), and 2001-143463 (U.S. Pat. No. 6,344,990 corresponding thereto) and Japanese Patent Publication No. 54-28252 (GB patent No. 1,502,334 corresponding thereto), etc. Also, as a technique concerning the DRAM of the two-intersection cell·two cells/bit method, Japanese Patent Laid-Open No. 7-130172 is disclosed.